Unix, python, perl, Linux, Tcl, Calibre, Back-End physical design EDA tools, large scale ASIC chip physical design, deep submicron ASIC design flow, Fusion Primetime

Linux Os, Synthesis, floorplanning, Cadence, LVS, Density, ECO implementation, Signal Integrity, SYN to GDS, clock tree, physical design verification, DRC, Antenna, Synopsys, EM IR analysis, formality verification

static timing analysis, timing signoff, Floor Planning, place-and-route, primetime, EDA tools and flows, SDC development, timing budgeting, RTL-to-GDS tools and methodologies, Synthesis, multi-power domain analysis, Clock Tree Synthesis, low-power design techniques

layout verification , static timing analysis, multiple power domain analysis, Floor Planning, custom IP and SoC designs, electrical rule checking, EDA Tools, Place And Route, static and dynamic power integrity, formal equivalence verification, structural design checking, physical design implementation, Power Clock Distribution, power and noise analysis, Synthesis, reliability verification, Dft, Clock Tree Synthesis

power integrity , DDR, Python, Routing, Perl, Tcl, IR drop, Signoff, primetime, Cadence Innovus, LVS, Timing Closure, SERDES, StarRC, Placement, Signal Integrity, Power Planning, floorplanning, Physical Verification, PNR, Physical Design, Timing congestion, DRC, PPA optimization, Reliability, Synopsys ICC2