static timing analysis, UNIX, Perl, Linux, Tcl, CAD software scripts, Synthesis, DFT RTL integration, Scan Insertion, Timing Analysis, ATPG verification, waveform debugging tools, Rtl Design, EDA tools methodology, test pattern generation, DFT design-for-test, Verilog simulator, equivalency checking, DFD design-for-debug, verification of DFx logic, DFT documentation, c-shell

static timing analysis, UNIX, Linux, Perl, Verilog, Debugging, Tcl, CAD software scripts, DFT design, Synthesis, DFD design, Scan Insertion, Timing Analysis, ATPG verification, Rtl Design, test pattern generation, equivalency checking, EDA Tools, verification of DFx logic, c-shell