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Showing 2 jobs
Skills:
static timing analysis, UNIX, Perl, Linux, Debugging, Tcl, CAD software scripts, DFT design, Synthesis, DFD design, Scan Insertion, Timing Analysis, ATPG verification, waveform debugging tools, Rtl Design, EDA tools methodology, test pattern generation, Verilog simulator, equivalency checking, verification of DFx logic, c-shell
Skills:
static timing analysis, UNIX, Linux, Perl, Verilog, Debugging, Tcl, CAD software scripts, DFT design, Synthesis, DFD design, Scan Insertion, Timing Analysis, ATPG verification, Rtl Design, test pattern generation, equivalency checking, EDA Tools, verification of DFx logic, c-shell
