We're expanding our Analog Mixed-Signal Design team and are looking for experienced Analog Mixed-Signal Circuit Design Engineers to join a long-term semiconductor project.
If you're passionate about designing next-generation analog IPs for advanced process technologies and enjoy solving challenging mixed-signal design problems, we'd love to hear from you.
Location: Malaysia (Onsite) penang
Employment: Permanent position with ThunderSoft
Hiring Timeline: Multiple openings available. Recruitment is ongoing and is expected to close by December 2026.
Key Responsibilities
- Design, simulate, and optimize high-performance analog and mixed-signal circuits.
- Develop and implement high-speed interface circuits, including Serializer/Deserializer (SerDes), DDR I/O, and other high-speed I/O designs.
- Design and verify clocking circuits such as PLLs, DLLs, and high-speed clock distribution networks.
- Design power management circuits including LDOs, Bandgap References, and perform power delivery network simulations.
- Design complex analog building blocks while meeting performance, power, and area requirements.
- Develop Analog RTL behavioral models to support system-level verification.
- Perform analog timing analysis and circuit performance validation.
- Conduct circuit simulation, verification, and optimization using Cadence Virtuoso/ADE and related EDA tools.
- Collaborate with layout, verification, and product engineering teams throughout the design cycle.
Required Qualifications
- Bachelor's, Master's, or Ph.D. in Electrical Engineering, Electronics Engineering, or a related discipline.
- Hands-on experience in analog and mixed-signal IC design.
- Strong knowledge in one or more of the following:
- SerDes I/O, DDR I/O, or other high-speed interface circuits
- PLL, DLL, and high-speed clock distribution
- LDO, Bandgap Reference, and power delivery simulation
- Pure analog and complex analog circuit design
- Analog RTL modeling
- Analog timing analysis
- Proficiency with Cadence design tools (ADE, Virtuoso, Spectre, and related EDA tools).
- Strong understanding of semiconductor device physics and advanced CMOS technologies.
Preferred Qualifications
- Experience designing on advanced process technologies of 7nm or below.
- Experience with 5nm or below Samsung process technologies is a strong advantage.
- Experience in full-custom analog layout collaboration and silicon bring-up is preferred.
Additional advantage:
Experience with Samsung 5nm (or below) process technology or layout experience will be considered a strong plus.
Experience Levels
We welcome engineers across multiple seniority levels:
- 2–4 years
- 4–6 years
- 6–8 years
- 8+ years
Why Apply
- Work on cutting-edge semiconductor technologies.
- Exposure to advanced process nodes (7nm).
- Long-term career opportunity with a global engineering team.
- Multiple openings available with excellent career growth.
If your background matches the above requirements, feel free to apply or send me your latest CV for a confidential discussion.
Please note: Due to the large hiring demand, interviews will be conducted on a rolling basis. Recruitment is expected to close by December 2026, and suitable candidates may be shortlisted before the closing date.
