Custom Layout Engineer

Our client in semiconductor industry is looking for an Analog IC Layout Engineer to support custom analog IP development and full-chip integration.

• 3–12 years of hands-on IC Custom Layout experience, with the ability to work independently or lead layout planning.
• Strong experience with TSMC process nodes, preferably advanced FinFET technologies (7nm, 5nm, or 3nm).
• Proven experience in custom Analog and High-Speed Mixed-Signal layout, including HSIO, SerDes (TX/RX), PLLs, VCOs, and Bandgap circuits.
• Strong knowledge of high-speed layout techniques, parasitic optimization, and sign-off verification, including EM, IR drop, ESD/Latch-up, and DRC/LVS closure.
• Strong English communication skills with the ability to collaborate effectively with circuit design engineers on post-layout (PEX) optimization.

For more information or confidential consultation, please do not hesitate to contact Athirah at [Confidential Information]

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Company Registration No.: 1080098-P (JTK License No: JTKSM 427)