We're looking for an experienced Digital Design Lead Engineer to drive end-to-end IP development for next-generation SoC products. If you're passionate about architecting and building digital IPs from scratch, we'd love to hear from you.
Key Responsibilities
- Lead digital IP/module development from concept, micro-architecture, RTL implementation, to SoC integration.
- Define hardware micro-architecture and develop functional specifications based on system requirements.
- Develop high-quality RTL, SDC timing constraints, and implement low-power designs using UPF.
- Collaborate closely with Architecture, Design Verification (DV), and Physical Design teams to achieve Performance, Power, Area (PPA), and timing targets.
Requirements
- Master's degree (or Bachelor's with equivalent experience) in Electrical & Electronics Engineering, Computer Engineering, or a related field.
- 5–10 years of hands-on experience in Digital IC / RTL Design.
- Proven experience delivering digital IP from specification through verified RTL.
- Experience in one or more of the following is highly preferred:
- CPU architecture, cache coherency, and AMBA AXI / CHI / ACE protocols.
- High-speed digital design, pipelining, and timing optimization.
- High-speed interface/protocol design (DDR, PCIe, USB, UCIe, or CXL).
- Pre-silicon simulation and post-silicon bring-up/debug.
- Mandarin proficiency is preferred to liaise with internal stakeholders.
