FPGA Design Engineer

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Job Description



Job Description

  • Participated in 2-3 SoC projects
  • Must have extensive experience in Micro-architecture design for SoC sub-blocks
  • Extensive experience in SoC RTL coding (Verilog or System-Verilog).
  • Experience in RTL Code Linting and CDC checks.
  • Experience in RTL integration using Industry standard tools, is an added advantage
  • Experience in low power design techniques
  • Good understanding of DFx design techniques
  • Good appreciation of AXI/AHB bus protocol, GigBE, USB, NAND Flash Technology, PCIe Gen2/3 Host interface, DDR2/3 memory interfaces etc.

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