FPGA Design experience
Experience with going through Iarge FPGAs through complete design cycle, from RTL and functional verification.
6+ years of RTL, - Verilog, System - Verilog, - VHDL experience
5+ years of FPGA design experience
Preferably with Perl and C Expertise with Synplify, - VCS, Modelsim and ISE tool
Experience with THC, USB2, microprocessor, eSPI, Audio at RTL Ievel will be plus Logic analyzer.
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