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Post-Silicon Memory Validation Staff Engineer
THE ROLE:
Processor silicon DDR interface feature enablement, electrical test and debug engineer. In this role, this senior level engineer will be part of a highly technical team that develops test plans, executes bring-up & feature enable, & debugs electrical issues in the memory sub-system of new processors.
THE PERSON:
The person needs to be well self-motivated for deliveries and innovation, strong technical background on DDR interface, also with good communication skills.
KEY RESPONSIBILITIES:
PREFERRED EXPERIENCE:
Job ID: 146587457
Skills:
System Engineering, Bash, Post silicon system validation, DDR validation, Triage and debug knowledge, DDR debug capability, Automation via Python, Platform level knowledge, Content development

Skills:
power supply , PowerShell, JIRA, Python, Logic Analyzer, Oscilloscope, PCIe high-speed bus debug, system-level stress test, BIOS firmware validation

Skills:
power supply , PowerShell, JIRA, Python, Logic Analyzer, Oscilloscope, system-level stress test, PCIe high-speed bus debug, BIOS firmware validation
Skills:
power supply , PowerShell, JIRA, Python, Logic Analyzer, Oscilloscope, PCIe high-speed bus debug, system-level stress test, BIOS firmware validation
Skills:
Test Plans, Perl, Ruby, Python, Linux, Scripting, logic analyzers, Debug, Oscilloscopes, software validation tools, electrical test, DDR interface, automation tool development