Senior Design Verification Engineer

• Minimum 5+ years of Design Verification experience
• Strong hands-on experience in IP or SoC verification
• Proficiency in SystemVerilog and Verilog
• Strong expertise in UVM-based verification environments
• Ability to independently build and debug IP / SoC verification testbenches

Core Technical Expectations

• Ownership of verification planning, execution, and closure
• Experience in testcase development, debugging, and root cause analysis
• Strong understanding of coverage-driven verification and closure metrics
• Ability to run and analyze regression suites
• Experience working closely with designers for issue resolution
• Ability to ensure verification completeness and signoff reporting

Highly Preferred

• High-speed interface verification experience:
• SerDes
• PCIe
• DDR
• HBM
• CPU verification experience (ARM / RISC-V)
• MCU / AI SoC verification exposure
• Experience improving verification productivity and automation flows
• Strong debugging and analytical mindset

Job Location: Penang, Malaysia

Interested candidates please share updated CV to [Confidential Information]

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