Senior Physical Design Engineer

Senior/ Lead Physical Design (PnR) Engineer

We are seeking experienced Senior / Lead Physical Design (PnR) Engineers to join our semiconductor design team. The successful candidates will lead the physical implementation of high-speed I/O PHYs on advanced technology nodes, ensuring designs meet aggressive performance, power, area (PPA), timing, and manufacturability goals. This role requires close collaboration with front-end designers, circuit designers, layout engineers, and methodology teams throughout the full chip implementation flow.

Key Responsibilities

• Lead the physical design implementation of high-speed PHY IPs, including SerDes, DDR I/O, and other high-speed interface blocks.
• Own the complete RTL-to-GDSII physical design flow, including:
• Floorplanning
• Power planning
• Placement
• Clock Tree Synthesis (CTS)
• Routing
• Timing closure
• Physical verification and signoff
• Drive PPA optimization while ensuring timing, signal integrity, power integrity, and reliability requirements are achieved.
• Perform and resolve design closure for setup/hold timing, congestion, IR drop, electromigration (EM), and DRC/LVS issues.
• Collaborate closely with RTL, analog, package, and verification teams to ensure successful integration and tape-out.
• Develop and improve physical design methodologies, automation scripts, and implementation flows.
• Mentor junior physical design engineers and provide technical leadership on project execution.
• Support silicon bring-up and post-silicon optimization when required.

Required Qualifications

• Bachelor's, Master's, or Ph.D. in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• 6+ years of hands-on experience in ASIC or SoC Physical Design (PnR).
• Strong experience implementing one or more of the following:
• SerDes PHY
• DDR PHY
• Other high-speed I/O PHYs
• Solid understanding of the complete Physical Design flow from floorplanning through signoff.
• Experience with advanced timing closure, clock distribution, power optimization, congestion analysis, and physical verification.
• Proficiency with industry-standard EDA tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, StarRC, and related physical design tools.
• Strong knowledge of scripting languages such as Tcl, Python, or Perl for design automation.

Preferred Qualifications

• Experience with advanced semiconductor process technologies of 7nm or below.
• Hands-on implementation experience using Samsung 5nm or below process technologies is a strong advantage.
• Experience with multiple successful tape-outs on advanced nodes.
• Familiarity with low-power design methodologies, high-speed interface implementation, and advanced package-aware physical design.

Desired Competencies

• Strong technical leadership and problem-solving skills.
• Excellent understanding of physical design challenges for high-performance and high-speed IPs.
• Ability to lead complex implementation activities and drive design closure under aggressive project schedules.
• Strong communication and collaboration skills across cross-functional engineering teams.
• Self-motivated with the ability to mentor junior engineers and contribute to methodology improvements.