HIRING SYSTEM VALIDATION ENGINEER
CONTRACT 1 YEAR
LOCAL MALAYSIAN CITIZEN ONLY
MAX SALARY BUDGET RM7,500
You will be involved in the IC validation, platform and infrastructure enablement works for high-speed FPGA/PLD devices that include some of the following responsibilities:
Compile existing design on different Quartus version and carry out regression testing on the FPGA
Generate dashboard report for the regression result and report out weekly to the project lead.
Debug on the regression result and do isolation of the issue to identify where the problem comes from.
LEVEL HIRING FOR