SYSTEM VALIDATION ENGINEER
Job Description
HIRING SYSTEM VALIDATION ENGINEER
CONTRACT 1 YEAR
LOCAL MALAYSIAN CITIZEN ONLY
MAX SALARY BUDGET RM7,500
Job description:
You will be involved in the IC validation, platform and infrastructure enablement works for high-speed FPGA/PLD devices that include some of the following responsibilities:
Compile existing design on different Quartus version and carry out regression testing on the FPGA
Generate dashboard report for the regression result and report out weekly to the project lead.
Debug on the regression result and do isolation of the issue to identify where the problem comes from.
Requirements:
BSEE/MSEE or equivalent
Good knowledge in FPGA architecture is an added advantage.
Experience in FPGA development tools such as Quartus.
Experience in developing test in programming languages such as python, tcl, C is an added advantage
BSEE/MSEE or equivalent
Good knowledge in FPGA architecture is an added advantage.
Experience in FPGA development tools such as Quartus.
Experience in developing test in programming languages such as python, tcl, C is an added advantage
JOB TYPE
Function
Roles
Education
Bachelors/ Degree
About
TekInfotree
About Recruiter
Anisha Kaur
Functions
Human Resources
Industry
Recruitment/Staffing/RPO
Skills/Roles
Electronic & Manufacturing
LEVEL HIRING FOR
Mid Level,
High Level
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