Interactive Debugger Jobs

Design Verification Engineer

Permanent Job

Bayan ,

Malaysia

3-5 years

Uvm RTL model build Coverage-based random constraint simulation Interactive debugger RTL simulators Formal Property Verification Testbench development Power-aware simulation System Verilog Ovm Shell Python Perl

6 days ago

Staff/Principal RTL Logic Design Engineer

Permanent Job

Bayan ,

Malaysia

8-10 years

RTL PCIe/USB/Ethernet LEC PCI-Express Sta micro-architecture VHDL Lint/CDC Dft UPF/CPF AMBA/OCP Usb Shell Verilog System Verilog Python Perl

6 days ago

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Interactive Debugger Jobs

Design Verification Engineer

Staff/Principal RTL Logic Design Engineer