Rtl Design Jobs

IP Logic Design Verification Engineer

Permanent Job

1-3 years

VHDL SoC System Solution Digital Design Rtl Design Hardware Debug IP Architecture Design Verification Timing Closure Verilog System Verilog

27 days ago

Sr Staff IP Design Engineer

Permanent Job

Penang ,

Malaysia

15-17 years

Rtl Design VHDL rtl verification Timing Analysis Linux/UNIX platforms Verilog System Verilog C Java Shell Scripts Perl

a month ago

FPGA Design Engineer

Contract Job

Penang

4-9 years

292 - 708 MYR monthly

Rtl Design RTL VHDL Design Engineer FPGA Design Verilog Perl Vcs Ise Usb

3 months ago

IP Validation Engineer

Permanent Job

Penang ,

Malaysia

3-5 years

Rtl Design Problem-solving Collaboration Innovation Analyzing Communication Validation High-speed IO IPs Initiative Usb System Verilog Pcie Debugging

a month ago

Senior IP Design Verification Engineer

Permanent Job

Kedah ,

Penang

5-7 years

Uvm power management Formal Rtl Design Verdi System Verilog Verilog Vcs Ovm Computer Architecture

a month ago

SIP Graduate Trainee Technical

Permanent Job

Penang ,

Malaysia

0-2 years

Rtl Design Timing Analysis PCI Express rtl verification Verilog System Verilog Perl Usb C++ Phyton Shell Scripts

a month ago

Senior Firmware Validation Engineer

Permanent Job

Kedah ,

Penang

5-7 years

Rtl Design power management Object-Oriented Programming Embedded Firmware Validation C++ Ruby Python Perl Computer Architecture

a month ago

IP Verification Engineer (Senior / Technical Leader)

Permanent Job

Penang

0-2 years

spyglass DDR4 Uvm Jasper Gold arm architecture cdc VHDL RDC analysis synthesis flow IP verification VC Spyglass risc-v Ovm Hdl Verilog Tcl Shell System Verilog Pcie Perl

a month ago

SIP Graduate Trainee Technical

Permanent Job

Penang ,

Malaysia

0-2 years

VHDL Verilog C Python Perl C++

a month ago

Physical Design

Permanent Job

Penang ,

Malaysia

2-4 years

Synthesis UPF low power design back-end activities Chip Finishing Antenna checks Physical Verification primetime power optimization IR drop Verbal Influencing Skills multi voltage checks 7 nm flows code scripts P&R Clock Tree Synthesis 14nm DRC architecture Design Compiler Physical design flow Tape-out flow Ability redhawk Dc convergence methodologies 10 nm Timing Closure written communication skills LVS Floorplan Layout Sta Rtl Design Primetime Knowledge communication Physical Design backend physical design IC Compiler Dft Expert Synopsys suite Tcl Perl

2 months ago

CPU-SoC Silicon Design Engineering Intern

Permanent Job

Kedah ,

Penang

0-2 years

SOC/PC Architecture Vlsi Design Unix System Verilog

a month ago

Software Developer- Circuit Simulation- Remote

Permanent Job

Malaysia

7-9 years

Numerical methods Sparse matrix techniques Verilog-A Object-oriented design Semiconductor C Python C++ Eda Linux Software Engineering

a month ago

Design Verification Architect

Permanent Job

Penang ,

Malaysia

15-17 years

OVM/UVM UPF RTL Sram SW Ip transceivers FPGAs I/Os Mentor/Siemens Questasim HW Synopsys VCS PCIe protocols Cadence Xcelium logic blocks Scrum Java Agile Development Verilog Tcl System Verilog Python

a month ago

SoC RTL Design Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

5-12 years

Xcelium RISC-V RTL spyglass AMBA Axi Modelsim Eda Vcs Soc Shell Perl Verilog Arm System Verilog Python Tcl

25 days ago

Top Industry

Job Category

Rtl Design Jobs

IP Logic Design Verification Engineer

Sr Staff IP Design Engineer

FPGA Design Engineer

IP Validation Engineer

Senior IP Design Verification Engineer

SIP Graduate Trainee Technical

Senior Firmware Validation Engineer

IP Verification Engineer (Senior / Technical Leader)

SIP Graduate Trainee Technical

Physical Design

CPU-SoC Silicon Design Engineering Intern

Software Developer- Circuit Simulation- Remote

Design Verification Architect

SoC RTL Design Engineer

ATE Test Program Development Engineer R&D (NPI)