routing, place-and-route, timing and SDC constraint generation, floorplanning, low-power design methodologies, Physical Verification, repeater insertion, chip-level floorplanning, feedthrough topology planning, top-level port pin assignment, power-aware synthesis, Timing Closure, Placement

Unix, python, perl, Linux, Tcl, Calibre, Back-End physical design EDA tools, large scale ASIC chip physical design, deep submicron ASIC design flow, Fusion Primetime

Tcl, Python, Perl, routing, Innovus, Timing Constraints, LVS, CTS, Sta, ICC2, Physical Design, primetime, Tempus, MCMM analysis, DRC, PNR, SDC