power integrity , Routing, Perl, Python, Tcl, Timing signal integrity, Power Planning, primetime, floorplanning, Cadence Innovus, SerDes PHY, DDR PHY, Timing Closure, StarRC, Placement, Reliability requirements, Physical verification and signoff, Synopsys ICC2, PPA optimization

High-Speed IO PHYs, advanced node layout rules ?7nm process technologies, DDR IO, Samsung ?5nm technologies, Physical Design PnR PD, SerDes IO