Python, scoreboarding, Mentor Questa, Cadence Xcelium, AXI protocol, GLS, SystemVerilog UVM, Synopsys VCS, memory controller architecture, assertions SVA, DDR protocol JEDEC specifications, functional coverage

Python, scoreboarding, Mentor Questa, Cadence Xcelium, AXI protocol, SystemVerilog UVM, GLS, Synopsys VCS, memory controller architecture, assertions SVA, DDR protocol JEDEC specifications, functional coverage

hardware engineering , Digital Logic Design, Embedded Firmware, Scripting Languages, Jtag, Verilog, System Verilog, IEEE1500, Micro-processor debug, Power management verification, Memory dump, MBIST, UPF, C Language, Scan dump, DFT architecture

cache coherency , Vcs, Perl, Python, Tcl, CHI, Ace, Xcelium, GPU Verification, AMBA protocols, NoC Integration, coverage-driven verification, SystemVerilog UVM, constrained-random verification, Performance Validation, Axi, Questa, SVA assertions