Job Details

Job Description:

DFx Micro-Architecture

Drive technical readiness (TR), that is understand customer requirement and further design relevant DFT/DFD/DFV features. DFT stand for Design for testability (testability from tester), DFD stand for Design for debug (Debug capability in Silicon or customer end ) and DFV stand for Design for validation ( validate effective with simple flow and method )
Architect and implement DFX strategy, These include provide uarch solution for TAP, Bscan, Scan, MBIST, IO DFX [ leakage, power, loopback ], debug port etc. for test testability and manufacturability.
Define DFx design methodology and uarch to ensure good coverage [ Scan and functional ] for IP and meet products DPM requirements
Overseeing the Scan/ATPG definition, design, verification, and documentation
Good and close loop communication across function group (Logic, Val, Ckt, SD, HVM ) to ensure a right DFX arch introduce to the IP.
Perform yield analysis improvement and assisting the silicon debug
Analyse product requirement to balance DFX requirements vs products PPA and cost.

DFx RTL Design

Require RTL coding, pick up different RTL tool-based solution. Integrate all other DFx sub-IPs into one stop. Along process will require signal/clock connection, timing convergence and etc.
Responsible to patch RTL logic for flawless area along execution phase. Ensure zero RTL design errors (bug free) as ultimate goal for DFx features.
Insert MemoryBIST logics, as part of the DFT features to enable High Volume Manufacturing (HVM) Memory screening through tests (Post Silicon team).
Collaborate with geo-diverse teams (CKT, structural design team, SOC/HVM ) in analysing, debugging and identifying the root cause of issues that arise.
Setup and debug Spyglass-DFT or other ATPG tools, generate ATPG patterns via Mentor Graphic Tessent or other equivalent tools, RTL and GLS test validation to ensure quality design, debug and root cause stuckat and atspeed failure using Mentor GLS testbench in Synopsys VCS tools, and validate chain test in serial testbench

DFx Validation

Provide direction and expectation on pre-silicon validation to ensure DFX feature are validated and all scenario are handled.
Collaborate closely with Post silicon PDE team to enable HVM (high volume manufacturing) testing capability.
Provide post silicon support to enable debug capability.

Others

Track progress of self/subteam to achieve goals timely
Provide indicators and guidance to management on issues and roadblocks on a timely basis

Qualifications

Requirement:

BS degree in Electrical Engineering, Computer Engineering or other related field of study with a minimum of 10+ years or MS degree with 8+ years of directly related industry experience in SOC/IP DFx Design and Verification.
Experience with creation of DFX plans, schedules and cost estimates for design/verification efforts
Experience in development of RTL design and validation of IP and SoC DFx.
Experience in working closely with physical design team to ensure timing closure for DFx logic.
RTL design of DFx IP , development of test env, test plan and test execution.
The ability work as an individual and as part of a team to deliver a product starting from the creation of the spec, design and verification.
Need a good understanding of System Verilog, scripting languages like shell scripting, PERL and verification methodologies like OVM, UVM and verification methodologies, sound understanding of test strategies, debug flows, ATPG tools and GLS.
Strong Si debug skills, ATE requirements and understanding of volume test requirements.
Strong Communications skills and the ability to effectively work with cross functional teams.
Very good knowledge of automation concepts and significant experience working on, DFD, TAP, STF, BIST, Scan, BSCAN
Should be able to contribute as IC or technically leading a group of team for a Focus faster DFX convergence.

Additional Qualifications Include

Familiar with UNIX, and well-versed in Verilog or C Programming
Knowledge in RTL integration and validation methodologies
Familiar with Scan design, methodology, coverage analysis and test validation
Ability to communicate well with counterparts and key stakeholders including cross-site partners

Job Type

Experienced Hire

Shift

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Business Group

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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