Routing, Pvs, PERL, Tcl, R3D, PEX, LVS, Layout Techniques, Verification, Skill Programming, CAD Tools, Calibre, Analog Layout, ERC, VCAR, DRC, VSR, virtuoso

FinFET technologies, Calibre, Mixed-Signal Layout, pegasus, DRC, Physical Verification, LVS, Analog Layout Design, Cadence Virtuoso

Signal integrity considerations, Analog Layout Design, Parasitic Extraction, Power distribution techniques, Analog circuit design principles

Python Programming, analytical statistical skills, schematic design and layout review, characterization of high-speed interfaces, validating protocols, usage of bench equipment, high-speed digital validation, validating and characterizing mixed-signal analog blocks, bench software development, knowledge of IAR Keil and other tool chains, performance benchmarks

Synopsys IC Validator, Calibre DRC LVS PEX, high-speed analog and mixed-signal layout design, Custom Compiler, LVS, Cadence Pegasus, DRC, Cadence Virtuoso Layout Suite, ERC checks, 7nm FinFET technology

synopsys tools , Analog Circuit Design, Mentor Siemens Calibre, Physical Verification, ERC, DRC, Custom Layout, LVS, Cadence Virtuoso, Analog Layout Design

Vdc, custom analog layout design, EDA Tools, Antenna, ADC, Circuit Design, RV high voltage flows, noise fixes, LDO, layout validation, Charge pump, density, DRCs, scripting skills, Vlsi Design, Virtuoso XL

ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques