Foundry design rules, Cadence Virtuoso Layout Suite, Parasitics coupling and noise mitigation, Reliability EM IR ESD awareness, Calibre DRC LVS PEX

Ant, Mentor Calibre, LVS, Latch-up, signal and clock shielding, EMIR, ERC, CMOS circuit theory, Esd, DRC, isolation techniques, Cadence Virtuoso, Reliability

device placement, DFM check, LVS, Place And Route, Floor Planning, matching and routing, reliability verification, tape out, layout optimization, post layout extraction, DRC, top level verification, full chip integration, parasitic analysis, Analog Layout, custom IPs