C, Usb, Makefile, Windows, Shell, Linux, Perl, Pcie, Verilog, Ethernet, Ruby, System Verilog, Systemc, IP level ASIC verification, UFS, UVM testbenches, power aware simulations, automating workflows in a distributed compute environment, Uvm, Axi, developing UVM based verification frameworks, debugging firmware and RTL code using simulation tools, TLM

Unix, perl, Ruby, Linux, Computer Architecture, Tcl, Synthesis, floor-planning, Verilog Hdl, interconnects, post-silicon validation, digital IP SoC development, Rtl Design, automating workflows, high-speed IO controller design, Timing Closure, Verification, ASIC design cycle, front-end EDA tools