UNIX, Debugging, Linux, Tcl, Perl, DFD design, test pattern generation, CAD software scripts, Timing Analysis, EDA tools methodology, ATPG verification, verification of DFx logic, Rtl Design, Verilog simulator, DFT design, waveform debugging tools, equivalency checking, Synthesis, c-shell, Scan Insertion

Verilog, UNIX, Linux, Tcl, static timing analysis, Perl, test pattern generation, CAD software scripts, Timing Analysis, ATPG verification, EDA Tools, Rtl Design, DFT design, DFD design, waveform debugging tools, equivalency checking, Synthesis, debug support, c-shell, DFT documentation, Scan Insertion