Unix, perl, Ruby, Linux, Computer Architecture, Tcl, Synthesis, floor-planning, interconnects, Verilog Hdl, post-silicon validation, digital IP SoC development, Rtl Design, automating workflows, high-speed IO controller design, Timing Closure, Verification, ASIC design cycle, front-end EDA tools

Unix, Linux, Perl, Computer Architecture, Ruby, Tcl, Digital IP SoC development, Interconnects, Post-silicon validation, Verilog Hdl, Front-end EDA tools, Verification, High-speed IO controller design, Rtl Design, Timing Closure, Synthesis, Floor-planning, ASIC design cycle, Automating workflows

Unix, perl, Ruby, Linux, Computer Architecture, Tcl, Synthesis, floor-planning, Verilog Hdl, interconnects, post-silicon validation, digital IP SoC development, Rtl Design, automating workflows, high-speed IO controller design, Timing Closure, Verification, ASIC design cycle, front-end EDA tools