static timing analysis, Perl, shell scripting, Verilog, Python, Tcl, Synthesis, Design Compiler, primetime, Fusion Compiler, IC Compiler II, Unix-based systems, Place And Route, Floor Planning, VHDL, physical design workflows, Clock Tree Synthesis

Unix, python, perl, Linux, Tcl, Calibre, Back-End physical design EDA tools, large scale ASIC chip physical design, deep submicron ASIC design flow, Fusion Primetime