UNIX, Linux, Tcl, static timing analysis, Perl, Scan Insertion, test pattern generation, CAD software scripts, Timing Analysis, EDA tools methodology, ATPG verification, Verilog simulator, Rtl Design, pattern debug support, waveform debugging tools, Synthesis, equivalency checking, DFD design-for-debug, c-shell, DFT documentation, DFT design-for-test, DFT RTL integration

static timing analysis, UNIX, Perl, Linux, Verilog, Debugging, Tcl, DFT design, Synthesis, DFD design, Scan Insertion, Timing Analysis, ATPG verification, Rtl Design, test pattern generation, equivalency checking, EDA Tools, verification of DFx logic, c-shell

Python, Routing, Perl, Tcl, CTS, primetime, ICC2, LVS, Physical Verification, Extraction, Placement, StarRC, STA timing closure, Synopsys Design Compiler, sub-10nm, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, ICC Fusion Compiler, 16nm, 14nm, Physical Design, Timing Closure, 12nm, DRC, PNR tools

redhawk , Apache, Tcl, Perl, Routing, Python, 16nm, EM, Ir, ICC Fusion Compiler, Physical Design, primetime, sub-10nm, Placement, 14nm, DRC, 12nm, Extraction, Power-plan Synthesis, CTS Timing Closure, LVS, Physical Verification, PNR tools, ICC2, Mentor Graphics Calibre, Crosstalk Analysis, STA timing closure, Synopsys Design Compiler, StarRC