Perl, Python, ASIC SOC design verification, Axi, AMBA, PCIe protocol, formal verification, Simulation model creation, AHB, APB bus, 8051 architecture

Usb, Perl, Pcie, Verilog, Ethernet, System Verilog, Tcl, UFS, High Speed IO Protocol IPs

Unix, python, perl, Linux, Tcl, Calibre, Back-End physical design EDA tools, large scale ASIC chip physical design, deep submicron ASIC design flow, Fusion Primetime