Scripting, C, Verilog, Python, Amplifiers, Analog Circuits Design, Transistor level circuit design, Synopsys primesim, Cadence Virtuoso, EMIR flows, Reliability, Bias circuits

Perl, Python, Tcl, CMOS Analog Circuit Design, StarRC, Calibre xRC, Assembler, ADE XL, Cadence Virtuoso, Spectre

MATLAB, Dll, Python, Automation Scripting, Hspice, Reliability, Clock and Data Recovery circuits, RX frontends circuits, Phase Interpolators, Verilog-A modeling, Spectre, Analog Circuit Design, AMS simulations, High-speed SerDes, PVT corners, Cadence Virtuoso ADE, Aging mismatch