UNIX, Linux, Tcl, static timing analysis, Perl, Scan Insertion, test pattern generation, CAD software scripts, Timing Analysis, EDA tools methodology, ATPG verification, Verilog simulator, Rtl Design, pattern debug support, waveform debugging tools, Synthesis, equivalency checking, DFD design-for-debug, c-shell, DFT documentation, DFT design-for-test, DFT RTL integration

static timing analysis, UNIX, Perl, Linux, Verilog, Debugging, Tcl, DFT design, Synthesis, DFD design, Scan Insertion, Timing Analysis, ATPG verification, Rtl Design, test pattern generation, equivalency checking, EDA Tools, verification of DFx logic, c-shell

UNIX, Debugging, Linux, Tcl, Perl, DFD design, test pattern generation, CAD software scripts, Timing Analysis, EDA tools methodology, ATPG verification, verification of DFx logic, Rtl Design, Verilog simulator, DFT design, waveform debugging tools, equivalency checking, Synthesis, c-shell, Scan Insertion

bist , boundary scan , Python, Verilog, System Verilog, Jtag, Cadence Modus ATPG, Analysis Tools, verification processes, EDA Tools, Mentor Tessent, Rtl Design, VHDL, Fault Simulation, automated test generation, DFT techniques, Synopsys DFT Compiler