static timing analysis, Perl, Python, EDA tools for synthesis, LINT, cdc, digital design principles, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, RTL quality tools such as Spyglass, RDC, VHDL, low-power design techniques

Power optimization techniques, Logic Synthesis, Digital circuit design principles, RTL Coding, Debugging and troubleshooting complex digital systems, Simulation and verification methodologies, Timing Analysis

static timing analysis, Synthesis, multi-power-domain design techniques, Simulation, Uvm, FPGA design methodologies

C, Fpga, Soc Architecture, Verilog, Scripting Languages, systemverilog, digital logic design principles, logic synthesis techniques, RTL design concepts, ASIC design methodologies, emulation platforms, low-power design techniques, assertion-based formal verification

Embedded Firmware, Fpga, Microprocessors, component obsolescence treatment, Hardware Verification, alternative solution identification, integration and validation testing, definition of electrical schematics, test procedures definition and execution, product performance evaluation, boards place route including signal integrity, troubleshooting skills on Electrical Electronic boards, Dft, hardware design development and testing, electronic design and development, DFM tools, Dfmea, Microcontrollers, product design board level testing, high-speed digital and analog electronic circuits, manufacturing failures analysis, Design and simulation tools

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation