Job Summary

Responsible for ensuring timing closure of complex ASIC/SoC designs by performing static timing analysis throughout the design cycle. Collaborate with RTL, synthesis, physical design, DFT, and signoff teams to optimize timing, power, and area while meeting performance targets.

Experience: 3+ years

Key Responsibilities

Perform block-level and full-chip static timing analysis (STA) using industry-standard EDA tools.
Analyze setup, hold, recovery, removal, and clock gating timing violations.
Drive timing closure across synthesis, place-and-route (PnR), and signoff stages.
Develop and validate timing constraints (SDC), timing exceptions, and clock definitions.
Perform timing debugging, root-cause analysis, and recommend RTL or physical design optimizations.
Collaborate with Physical Design engineers to optimize timing through placement, CTS, buffering, and routing improvements.
Analyze cross-talk, on-chip variation (OCV/AOCV/POCV), IR drop, and signal integrity impacts on timing.
Support multi-mode multi-corner (MMMC) timing analysis and signoff.
Review timing reports and ensure compliance with design specifications.
Develop scripts (Tcl, Python, Perl, or Shell) to automate STA analysis and reporting.
Participate in design reviews and provide timing signoff recommendations.

Required Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
Strong understanding of digital IC design fundamentals.
Experience with Static Timing Analysis methodologies.
Knowledge of CMOS timing, clock distribution, timing constraints, and timing closure techniques.
Familiarity with synthesis and physical implementation flows.
Proficiency in scripting (Tcl preferred, Python/Perl/Shell is a plus).

Preferred Tools

Synopsys PrimeTime
Cadence Tempus
Synopsys Design Compiler
Cadence Innovus
Synopsys ICC2
PrimeTime SI
PrimeTime PX
Verdi or SimVision
Linux/Unix environment
Git or other version control systems

Preferred Skills

Experience with advanced technology nodes (7nm, 5nm, 3nm, etc.).
Knowledge of MMMC, OCV/AOCV/POCV, SI, EM/IR, and power analysis.
Strong debugging and analytical skills.
Good communication and cross-functional collaboration.
Ability to work in a fast-paced product development environment.

Physical Design STA Engineer