System Verilog, SystemVerilog Assertions, Functional Code Coverage, Bluetooth BLE Technologies, constraint random tests, HDLs like Verilog, SV UVM environments, Formal checks, debugging RTL TB issues using Verdi or similar tools, Functional Verification, SoC Integration

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Verilog, random stimulus, VMM, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, systemverilog

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, UCIe, Uvm, systemverilog, AMBA, Axi

System Verilog, Building test benches from scratch, ASIC verification using UVM

Fpga, Perl, Python, low power verification, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, RTL development environments, test bench infrastructure, transaction level modelling, verification platforms, formal verification methods, emulation platforms

.NET, Java, Javascript, Python, OpenAPI Generator, GitHub Actions, Go, templating frameworks