redhawk , Tcl Scripting, primetime, Fusion Compiler, ICC2, Conformal, LVS, Physical Design, electro-migration checks, Calibre, multi voltage high frequency designs, Floor Planning, custom polygon editing, synthesis APR flows, Formal equivalence, CPU physical design, Dce, Cadence Tools, StarRCXT, Timing Verification, Timing Closure, DRC, DCT, ICV, Noise cross-talk OCV analysis

STA timing optimization, CTS and global clock distribution methods, power rollup methodology, Synthesis, Physical Verification, constraints generation, Place And Route, Timing Closure, Extraction, floorplanning

Tcl Scripting, Innovus, PNR Timing closure, Fusion Compiler, Physical signoff

LINUX, Routing, UNIX, PERL, Static Timing Analysis, Tcl, Cadence PVS, ETS, Design Compiler, Power distribution planning, Cadence Innovus, ASIC development, VDSM process technology, Physical Design, Timing Closure, Signal Power Integrity, Synopsys ICC, Genus, Floor Planning, HDL Verilog, Prime Time, Low Power methodology

Routing, primetime, Physical implementation, Placement, Floor Planning, Optimization

Tcl, Perl, Routing, Python, Apache Redhawk, EM, Ir, ICC Fusion Compiler, Physical Design, primetime, sub-10nm, Placement, 14nm, DRC, 12nm, Extraction, 16nm, Power-plan Synthesis, LVS, Physical Verification, CTS, PNR tools, ICC2, Mentor Graphics Calibre, Crosstalk Analysis, Timing Closure, STA timing closure, Synopsys Design Compiler, StarRC

redhawk , Apache, Tcl, Perl, Routing, Python, 16nm, EM, Ir, ICC Fusion Compiler, Physical Design, primetime, sub-10nm, Placement, 14nm, DRC, 12nm, Extraction, Power-plan Synthesis, CTS Timing Closure, LVS, Physical Verification, PNR tools, ICC2, Mentor Graphics Calibre, Crosstalk Analysis, STA timing closure, Synopsys Design Compiler, StarRC