We are seeking talented Analog Mixed-Signal Circuit Design Engineers to join our IC design team. The successful candidates will contribute to the design and development of high-performance analog and mixed-signal circuits for advanced semiconductor technologies. This role offers the opportunity to work on cutting-edge process nodes and collaborate with cross-functional engineering teams to deliver industry-leading silicon solutions.

Key Responsibilities

Design, simulate, and optimize high-performance analog and mixed-signal circuits.
Develop and implement high-speed interface circuits, including Serializer/Deserializer (SerDes), DDR I/O, and other high-speed I/O designs.
Design and verify clocking circuits such as PLLs, DLLs, and high-speed clock distribution networks.
Design power management circuits including LDOs, Bandgap References, and perform power delivery network simulations.
Design complex analog building blocks while meeting performance, power, and area requirements.
Develop Analog RTL behavioral models to support system-level verification.
Perform analog timing analysis and circuit performance validation.
Conduct circuit simulation, verification, and optimization using Cadence Virtuoso/ADE and related EDA tools.
Collaborate with layout, verification, and product engineering teams throughout the design cycle.

Required Qualifications

Bachelor's, Master's, or Ph.D. in Electrical Engineering, Electronics Engineering, or a related discipline.
Hands-on experience in analog and mixed-signal IC design.
Strong knowledge in one or more of the following:
SerDes I/O, DDR I/O, or other high-speed interface circuits
PLL, DLL, and high-speed clock distribution
LDO, Bandgap Reference, and power delivery simulation
Pure analog and complex analog circuit design
Analog RTL modeling
Analog timing analysis
Proficiency with Cadence design tools (ADE, Virtuoso, Spectre, and related EDA tools).
Strong understanding of semiconductor device physics and advanced CMOS technologies.

Preferred Qualifications

Experience designing on advanced process technologies of 7nm or below.
Experience with 5nm or below Samsung process technologies is a strong advantage.
Experience in full-custom analog layout collaboration and silicon bring-up is preferred.

Experience Levels (Hiring Plan)

2–4 years: 2 openings
4–6 years: 4 openings
6–8 years: 4 openings
8+ years: 4 openings