C, Verilog, Perl scripting, Python, Axi, Uvm, AHB, systemverilog

Python, Tcl, timing sign-off, PDV, Physical Design, place-and-route analysis, Cadence Innovus, Siemens Mentor Calibre, advanced technology nodes 5nm or lower

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, UCIe, Uvm, systemverilog, AMBA, Axi

C, Python, LabVIEW, Analog Digital and Mixed-signal validation lab equipment, signal generators, SMUs

Usb, C, Uart, Bash, Spi, Pcie, Perl, Verilog, I2c, System Verilog, Python, Tcl, gate-level simulations, verification methodology, i2s, Uvm, DP, Sd

Python, systemverilog, Analog Mixed-Signal circuits, EDA Tools, Verilog-A, Cadence