Python, Tcl, timing sign-off, PDV, Physical Design, place-and-route analysis, Cadence Innovus, Siemens Mentor Calibre, advanced technology nodes 5nm or lower

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, UCIe, Uvm, systemverilog, AMBA, Axi

static timing analysis, Perl, Python, EDA tools for synthesis, LINT, cdc, digital design principles, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, RTL quality tools such as Spyglass, RDC, VHDL, low-power design techniques

C, Vcs, Jtag, Perl, Verilog, Python, Tcl, Verdi, MBIST, DFT micro-architecture, Synopsys Tetramax, EDA Tools, Scan, Mentor Tessent

Excel, Python, Ms Word

Tensorflow, Machine Learning, Pytorch, Linux, Python, Pytest, Deep Learning, Transformers

Java, Automated Testing, Oauth, Typescript, React, Distributed Systems, Python, Apis, Sso, platform engineering, authentication and authorization, AI agents, event-driven systems, observability, intelligent automation platforms, cloud-native architectures, LLM-powered applications