Questa, JasperGold, VC Formal

Python, Tcl, timing sign-off, PDV, Physical Design, place-and-route analysis, Cadence Innovus, Siemens Mentor Calibre, advanced technology nodes 5nm or lower

Perl, Verilog, Python, Arm CoreSight IP, power clock domain crossing, reset domain crossing, ARM-based designs, systemverilog

Java, Golang, Gcp, Terraform, Docker, Linux, Ansible, Azure, Kubernetes, Python, AWS, Java Spring Boot

C, Windows, Network Programming, Linux, Perl, Object Oriented Design, Python, Cross-platform development, NoSQL databases, Multithreaded concepts, Communication Protocols, Build process, High-speed message queues, Real-time systems

.NET, Java, Javascript, Python, OpenAPI Generator, GitHub Actions, Go, templating frameworks

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, UCIe, Uvm, systemverilog, AMBA, Axi

Machine Learning, Cloudformation, Deep Learning, MLops, Terraform, Data Architecture, Data Governance, Security Compliance, Python, AWS, Generative AI, Infrastructure as Code, AWS Bedrock, AWS CDK, MLflow, AWS SageMaker