control logic , Verilog, Sta, Synthesis, PCS link training, IEEE 802.3 Ethernet, state machines, systemverilog, cdc, RDC, Rtl Design

power optimization , Static Timing Analysis, Design-for-Debug, SoC Debug architectures, low power design techniques, constraints development for Physical Design implementation, SoC integration, Design-for-Test, power analysis

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation

Spi, Verilog, I2c, System Verilog, Scan Insertion, Digital DFT design, Logicbist, Cadence, Mentor, TetraMax, AMBA, Gate level simulations, Synthesis, ATPG, Digital RTL coding, Synopsys, PMIC

Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC