Tcl, Python, Perl, systemverilog, System Verilog Assertions, Emulation

Usb, C, Pcie, Verilog, Ethernet, Python, Zebu, Protium, Palladium, systemverilog

Perl, Verilog, Python, Tcl, formal verification with Cadence LEC, Netlist CLP, Spyglass Lint CDC checks, UPF, clock domain crossing designs, Rtl Design, Synthesis, Logical Equivalence checks, low power design methodology

C, Uart, Bash, Spi, DDR, Pcie, Perl, Verilog, I2c, Python, System Verilog, Tcl, i2s, DFX Verification, Uvm, Axi, APB, AHB

Vcs, Jtag, Pcie, Awk, I2c, Python, Jasper, Sed, Perl, Networking Protocols, Ethernet, PLLs, Uvm, Co-Simulations, GLS, AXI4.0, Verdi, debugs, Emulation Platforms, Test Bench Accelerators, Coverage Driven Methodology, systemverilog, Ate, HW SW Flow

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

C++, Soc, Communication engineering, Simulation, Asic verification, Uvm