Ovm, Verilog, System Verilog, C, Systemc, PERL, Shell script, Assembly Language, dpi, SoC Verification, Uvm, Emulation

protocol stack , Gerrit, Networking, Qos, Ip Routing, Python, Java, Bash, Jenkins, Git, Linux, Integration, Lte, switching, latency, QoE, CI CD, system-level verification, traffic generation, KPIs, throughput, Deployment, Resource Utilization, 5G New Radio NR, Channel emulators, Troubleshooting, RAN architecture, Test Tools, Performance Analysis

bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components

Tcl, Python, Perl, systemverilog, Functional Verification, UVM methodology, High-speed networking interfaces, Coverage-driven verification, Ethernet IPs, Emulation platforms or FPGA prototyping

Perl, Verilog, Python, advanced verification methodologies like e-specman SV-UVM, debug tools like Indago GDB, SV scripting languages, Cadence or equivalent simulation tools

JIRA, Jenkins, Analyzing verification issues, Intel Quartus, Xilinx Vivado, FPGA design and verification following the DO-254 process, Interpreting schematics and layout diagrams, RTL design using VHDL, Electronic components and circuit design flow, Microchip Libero SoC