We're expanding our advanced semiconductor engineering team and are looking for experienced Senior Staff / Lead Physical Design (PnR) Engineers to join a cutting-edge chip development project.

If you have strong expertise in Place & Route (PnR) for High-Speed IO PHYs and enjoy working on advanced process technologies, we'd love to hear from you.

Location: Malaysia (Onsite)

Employment: Permanent position with ThunderSoft

Hiring Timeline:4 openings available. Recruitment is expected to close by December 2026, and interviews will be conducted on a rolling basis.

What You'll Do

As a Senior Physical Design Engineer, you will be responsible for the physical implementation of advanced High-Speed Interface IPs on leading-edge process technologies.

Responsibilities include:

Physical Design (PnR) implementation for High-Speed IO PHYs
Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, and Physical Optimization
Timing closure, congestion analysis, and physical signoff support
Work closely with RTL, Circuit Design, Layout, and Verification teams to achieve successful tape-out
Drive backend design quality, performance, power, and area optimization
Support advanced node implementation from netlist to GDSII

Requirements

Bachelor's or MasterKey Responsibilities

Lead the physical design implementation of high-speed PHY IPs, including SerDes, DDR I/O, and other high-speed interface blocks.
Own the complete RTL-to-GDSII physical design flow, including:
Floorplanning
Power planning
Placement
Clock Tree Synthesis (CTS)
Routing
Timing closure
Physical verification and signoff
Drive PPA optimization while ensuring timing, signal integrity, power integrity, and reliability requirements are achieved.
Perform and resolve design closure for setup/hold timing, congestion, IR drop, electromigration (EM), and DRC/LVS issues.
Collaborate closely with RTL, analog, package, and verification teams to ensure successful integration and tape-out.
Develop and improve physical design methodologies, automation scripts, and implementation flows.
Mentor junior physical design engineers and provide technical leadership on project execution.
Support silicon bring-up and post-silicon optimization when required.

Required Qualifications

Bachelor's, Master's, or Ph.D. in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
6+ years of hands-on experience in ASIC or SoC Physical Design (PnR).
Strong experience implementing one or more of the following:
SerDes PHY
DDR PHY
Other high-speed I/O PHYs
Solid understanding of the complete Physical Design flow from floorplanning through signoff.
Experience with advanced timing closure, clock distribution, power optimization, congestion analysis, and physical verification.
Proficiency with industry-standard EDA tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, StarRC, and related physical design tools.
Strong knowledge of scripting languages such as Tcl, Python, or Perl for design automation.

Preferred Qualifications

Experience with advanced semiconductor process technologies of 7nm or below.
Hands-on implementation experience using Samsung 5nm or below process technologies is a strong advantage.
Experience with multiple successful tape-outs on advanced nodes.
Familiarity with low-power design methodologies, high-speed interface implementation, and advanced package-aware physical design.

Desired Competencies

Strong technical leadership and problem-solving skills.
Excellent understanding of physical design challenges for high-performance and high-speed IPs.
Ability to lead complex implementation activities and drive design closure under aggressive project schedules.
Strong communication and collaboration skills across cross-functional engineering teams.
Self-motivated with the ability to mentor junior engineers and contribute to methodology improvements.

Experience Levels (Hiring Plan – 4 engineers needed)

6–8 years: 2 openings (Senior Engineer)
8+ years: 2 openings (Lead Engineer)

Why Join Us

Work on next-generation High-Speed Interface IPs.
Exposure to advanced semiconductor process technologies.
Collaborate with experienced global engineering teams.
Long-term career opportunity with strong technical ownership and growth.

If your experience aligns with the above, we'd love to connect. Please apply directly or send me your latest CV for a confidential discussion.

Recruitment is expected to close by December 2026. Early applications are highly encouraged as interviews are conducted on a rolling basis.

Senior Staff / Lead Physical Design (PnR) Engineer | Advanced Node ( 7nm) | Malaysia