Shell, Perl, Debugging Tools, Python, verification methodologies, ASIC SOC verification, CPU GPU architecture or verification, Uvm, systemverilog

perl scripting, Jasper, Verilog, System Verilog, digital systems, assembly x86 code, VSI-FV, IEV, IFV, CPU verification, Formal Verification methodology

C, Makefile, Hdl Programming, Perl, Verilog, Computer Architecture, Ruby, Python, System Verilog, AI tools, Functional Verification, UNIX software environment, simulation and debugging, logic simulation, Assembly Programming

perl scripting, Jasper, Verilog, System Verilog, digital systems, assembly x86 code, VSI-FV, IEV, IFV, CPU verification, Formal Verification methodology

C, Makefile, Hdl Programming, Perl, Verilog, Computer Architecture, Debugging, Ruby, Python, System Verilog, AI tools, Functional Verification, UNIX software environment, logic simulation, Assembly Programming, CPU cache memory subsystem verification

Python, Tcl, timing sign-off, PDV, Physical Design, place-and-route analysis, Cadence Innovus, Siemens Mentor Calibre, advanced technology nodes 5nm or lower

Vcs, Verilog, Scripting Languages, Debug, verification methodologies, Simulation, Uvm, coverage infrastructure tools, VHDL, stimulus checking, NC, Verilator