Git, Bitbucket, Verilog, Visualstudio, Python, System C, Uvm, systemverilog

Perl, Verilog, Python, spyglass, VHDL, DDR memory controllers, PCIe protocols

PERL, Python, Tcl, Sta, RTL-GDS flows, Physical Verification, SNPS CAD Flow, SNPS CDNS-based tools

Fpga, Logic Design, Verilog, Uvm, Timing Constraints, TCL scripts, regression frameworks, Timing Analysis, Power product design, System-Verilog, RTL Coding, Functional Verification, Sta, micro-architecture, ATPG generation, formal verification, synthesis scripts, Synthesis, ABV, design constraints, Digital Verification, Scan Insertion

IP SoC verification, ASIC-SoC design verification, systemverilog