Tcl, Python, Perl, routing, Innovus, Timing Constraints, LVS, CTS, Sta, ICC2, Physical Design, primetime, Tempus, MCMM analysis, DRC, PNR, SDC

routing, place-and-route, timing and SDC constraint generation, floorplanning, low-power design methodologies, Physical Verification, repeater insertion, chip-level floorplanning, feedthrough topology planning, Timing Closure, top-level port pin assignment, power-aware synthesis, Placement

Cadence Innovus, STA concepts, Synopsys ICC2, Timing Closure, Physical Design, Logic synthesis concepts, Physical Design signoff requirements, Place Route