OASIS, Verilog, Python, Shell, Perl, Tcl, PERC, LVS, CDL, Dfm, SVRF-based automation, XOR methodologies, antenna density, ASIC physical verification, Spice, Cadence Pegasus, DEF, LEF, Siemens Calibre nmDRC, metal-fill, ERC, DRC, Synopsys ICV, GDSII

DDR, Usb, Pcie, Ethernet, SV, CXL, Uvm

System Verilog, Systemc, UVM based verification, ARM bus protocols

AI ML techniques, Uvm, systemverilog, Coverage-driven verification

Tcl, Python, Perl, systemverilog, System Verilog Assertions, Emulation

C, Fpga, Python, Perl, Uvm, RTL, AMBA bus protocols, systemverilog, Emulation platforms, Automation scripts, Transaction level modeling

Networking, Specman E, digital logic, Constrained-random verification, IP subsystem SoCs, Debug, Verification, systemverilog

Verilog, System Verilog, Asic verification, Uvm, cpu design, DDR4, Memory

Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, systemverilog, UPF management