Fpga, Usb, Python, Pcie, Perl, Emulation, directed constrained-random tests, Uvm, AXI4, coverage driven verification, Test Bench, verification methodologies, systemverilog, transaction level modeling, AMBA, MIPI, formal verification

Networking, Specman E, digital logic, Constrained-random verification, IP subsystem SoCs, Debug, Verification, systemverilog

Verilog, System Verilog, Asic verification, Uvm, cpu design, DDR4, Memory

Verilog, System Verilog, VHDL, Xcelium, Questa, Simulator exposure with VCS, Proficient in simulation and HW languages, Uvm, UVVM

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

System Verilog, Building test benches from scratch, ASIC verification using UVM

Doors, Tcl Scripting, FPGA Synthesis Place and Route, DO-254 development process, RTL development using VHDL, Hardware system design knowledge of digital logic, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, FPGA design tools like Libero, Electronics Electrical Engineering, Knowledge of Hardware Board and different components like ADC DAC Serial Memory