Unix, python, perl, Linux, Tcl, Calibre, Back-End physical design EDA tools, large scale ASIC chip physical design, deep submicron ASIC design flow, Fusion Primetime

Linux Os, Synthesis, floorplanning, Cadence, LVS, Density, ECO implementation, Signal Integrity, SYN to GDS, clock tree, physical design verification, DRC, Antenna, Synopsys, EM IR analysis, formality verification

Routing, Perl, Python, Tcl, Netlist to GDSII, floorplanning, LVS, Partitioning, ERC, Placement, Antenna checks, Low-power implementation techniques, DRC, IR-drop analysis

rc extraction , Placement, Routing and Optimization, Physical Design, Timing ECOs, Timing Closure, floorplanning, Timing ECO Implementation, Full-chip and Block-level Physical Implementation

layout verification , static timing analysis, Pcie, Floor Planning, EDA Tools, electrical rule checking, Place And Route, SIP logic partition, static and dynamic power integrity, physical planning and design, formal equivalence verification, structural design checking, physical design implementation, Power Clock Distribution, power and noise analysis, Synthesis, design optimization, reliability verification, Clock Tree Synthesis