power optimization , static timing analysis, routing, Verilog, Synthesis, power distribution analysis, submicron process node technologies, power delivery methodologies, Power Estimation, reliability verification, formal verification, VHDL, Placement, low-power design techniques, timing signoff, Clock Tree Synthesis

Unix, Perl, Linux, Tcl, Low power verification, Placement, floorplanning, power analysis, PNR implementation

routing, Sta, CTS, ECO execution, Pv, floorplanning, Dfm, constraints synthesis, Dft, Si, Timing Closure, block-level PnR, Netlist to GDS flow

C, Embedded Linux, Debugging, Automation Frameworks, Linux, Shell scripting, Firmware Development, Python, Embedded Software Development, Boot flows, Customer Engineering, Firmware initialization, Applications Engineering, Security, Embedded Systems, power management, Firmware architecture, Platform management functions, Platform Engineering

redhawk , Routing, Perl, Python, Tcl, SDC constraints, Design Compiler, CTS, primetime, Fusion Compiler, RTL-to-GDS implementation, Voltus, ECO implementation, Full Chip Physical Design, Synthesis, MCMM timing closure, Physical Design methodologies, EM IR analysis, Synopsys ICC2

routing, Verilog, Floor Planning, VHDL, Placement, Physical Verification, Clock Tree Synthesis, RTL to GDS flows

Static Timing Analysis, Frontend, Asic, Timing Closure, Physical Verification