AI ML techniques, Uvm, systemverilog, Coverage-driven verification

Fpga, Usb, Python, Pcie, Perl, Emulation, directed constrained-random tests, Uvm, AXI4, coverage driven verification, Test Bench, verification methodologies, systemverilog, transaction level modeling, AMBA, MIPI, formal verification

Usb, C, Pcie, Verilog, Ethernet, Python, Zebu, Protium, Palladium, systemverilog

Networking, Specman E, digital logic, Constrained-random verification, IP subsystem SoCs, Debug, Verification, systemverilog

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Hmc, Arm, Ethernet, Pcie, DDR, Functional Safety verification, formal verification, Assertions, UCIe, Uvm, Security verification, systemverilog, Emulation, coverage-driven verification, SoC Verification, AI-assisted verification, RISC-V, Portable Stimulus PSS, Zebu, HBM, Palladium, Hardware software co-verification, Veloce