Version Control, configuration management, PERL, Python, Tcl, AI tools, PPA, multi-patterning, Skill, LVS, cell layout optimization, flow automation, DRC, Cadence Virtuoso

redhawk , Verilog, Fusion Compiler, Metal-only ECO Implementation, Timing Optimization, Signal Integrity Analysis, FLASH Process Technologies, Floorplan Exploration, Innovus, Calibre, low power design, GDSII Flow, VHDL, Physical Design, Starrcxt, Reliability Analysis, Clock Tree Synthesis

routing, Sta, CTS, ECO execution, Pv, floorplanning, Dfm, constraints synthesis, Dft, Si, Timing Closure, block-level PnR, Netlist to GDS flow

layout verification , System Verilog, Computer Engineering, Tcl, ASIC Design, Electrical Engineering, Computer Science, design rules, low power designs

Scripting, Perl, Tcl, Calibre, Innovus, Assura, Cv, ICC2, Cadence, EDA Tools, Verification Tools

redhawk , Tcl, Perl, Python, SDC, Foundry PDKs, Implementation tool suite, EDA Tools, Power gating, Cadence, primetime, Tempus, Synopsys ICC2, CPF, Timing Analysis, TSMC, Physical Design, Synopsys, UPF, Cadence Innovus, Sta, Multi-voltage domains, Voltus, Signoff tools, Samsung, Low-power design techniques

redhawk , Routing, Perl, Python, Tcl, SDC constraints, Design Compiler, CTS, primetime, Fusion Compiler, RTL-to-GDS implementation, Voltus, ECO implementation, Full Chip Physical Design, Synthesis, MCMM timing closure, Physical Design methodologies, EM IR analysis, Synopsys ICC2

Python, Tcl, floorplanning, Physical design flows, Logical Equivalence, Clock CTS, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route

Physical Design, DFT Implementation, Layout Extraction, Rtl Design