Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, AMBA protocols, Uvm, systemverilog

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

DFT architecture, coverage analysis, Memory-BIST, ATPG pattern generation, compression at core level, Scan Insertion, SSN architecture, clock architecture, timing simulations, no-timing simulations, occ

Perl, Python, Tcl, Clock domain partitioning, Power integrity and power-aware physical implementation, Block and subsystem-level physical design flows, primetime, Fusion Compiler, Clock gating, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Azure - AKS, Python, Sql, Github, Docker, Arm

Software Release Management, Shell scripting, Deployment Git, WLAN standards IEEE 802.11, Automation using Python

arm architecture , Usb, DDR, Perl, Pcie, Test Plan, Scripting, Python, Shell Programming, Tcl, Arm core, GIC, SMMU, Dms, verification checks, Arm system IP, verification plan, debug methodology, SoC Verification